Section 5.1: Device Structure and Physical Operation
5.1
An NMOS transistor is fabricated in a
0.13μm CMOS
process with
$L=1.5{L}_{\text{min}}$
and
$W=1.3$
μm. The process technology
is specified to have
${t}_{ox}=2.7$
nm,
${\mu}_{n}=400$
cm
${}^{2}$/V·s,
and
${V}_{tn}=0.4$
V.
(a) Find
${C}_{ox}$,
${k}_{n}^{\text{'}}$,
and
${k}_{n}$.
(b) Find the overdrive voltage
${V}_{OV}$
and the minimum value of
${V}_{DS}$
required to operate the transistor in saturation at a current
${I}_{D}=100$
$\mu $A.
What gatetosource voltage is required?
(c) If
${v}_{DS}$
is very small, what values of
${V}_{OV}$
and
${V}_{GS}$
are required to operate the MOSFET as a
$\text{2k}\Omega $
resistance? If
${V}_{GS}$
is doubled, what
${r}_{DS}$
results? If
${V}_{GS}$
is reduced, at what value does
${r}_{DS}$
become infinite?
(b) When the MOSFET operates in saturation, we have
$${I}_{D}={\displaystyle \frac{1}{2}}{k}_{n}{V}_{OV}^{2}$$ 
$${V}_{DS\text{min}}=0.24\text{V}$$ 
$${V}_{GS}={V}_{tn}+{V}_{OV}=0.4+0.24=0.64\text{V}$$ 
$${i}_{D}\simeq {k}_{n}{V}_{OV}\phantom{\rule{2pt}{0ex}}{v}_{DS}$$ 
$${r}_{DS}\equiv {\displaystyle \frac{{v}_{DS}}{{i}_{D}}}=1\mathrm{\u2215}{k}_{n}{V}_{OV}$$ 
$${V}_{GS}=0.4+0.15=0.55\text{V}$$ 
$${V}_{GS}=2\times 0.55=1.1\text{V}$$ 
$${V}_{OV}=1.10.4=0.7\text{V}$$ 
$${V}_{GS}={V}_{tn}=0.4\text{V}$$ 
Section 5.2: Current–Voltage Characteristics
5.2
An NMOS transistor fabricated in a 0.13μm
process has
$L=0.2$
μm and
$W=2$
μm. The process
technology has
${C}_{ox}=12.8$
fF/μm
${}^{2}$,
${\mu}_{n}=450$
cm
${}^{2}$/V·s,
and
${V}_{tn}=0.4$
V. Neglect the channellength modulation effect.
(a) If the transistor is to operate at the edge of the saturation region with
${I}_{D}=100$
μA,
find the values required of
${V}_{GS}$
and
${V}_{DS}$.
(b) If
${V}_{GS}$
is kept constant at the value found in (a) while
${V}_{DS}$
is changed, find
${I}_{D}$
that results at
${V}_{DS}$
equal to half the value in (a) and at
${V}_{DS}$
equal to 0.1 the value in (a).
(c) To investigate the operation of the MOSFET as a linear amplifier, let the operating point
be at
${V}_{GS}=0.6$
V and
${V}_{DS}=0.3$
V. Find the change in
${i}_{D}$
for
${v}_{GS}$
changing from 0.6 V by
$+10$
mV and by
$10$
mV. Comment.
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}{\mu}_{n}{C}_{ox}\left({\displaystyle \frac{W}{L}}\right){V}_{OV}^{2}$$ 
$${V}_{GS}={V}_{tn}+{V}_{OV}=0.4+0.186=0.586\text{V}$$ 
$${V}_{DS}={V}_{DS\text{min}}={V}_{OV}=0.186\text{V}$$ 
$${v}_{GS}=0.6+0.010=0.610\text{V}$$ 
$$\mathrm{\u25b3}{i}_{D}=127115.2=11.8\mu \text{A}$$ 
$${v}_{GS}=0.60.010=0.590\text{V}$$ 
$$\mathrm{\u25b3}{i}_{D}=104115.2=11.2\phantom{\rule{2pt}{0ex}}\mu \text{A}$$ 
5.3
Figure 5.3.1
An NMOS transistor fabricated in a process for which the process transconductance parameter is 400 $\mu $A/V ${}^{2}$ has its gate and drain connected together. The resulting twoterminal device is fed with a current source $I$ as shown in Fig. 5.3.1. With $I=40$ $\mu $A, the voltage across the device is measured to be 0.6 V. When $I$ is increased to 90 $\mu $A, the voltage increases to 0.7 V. Find ${V}_{t}$ and $W\mathrm{\u2215}L$ of the transistor. Ignore channellength modulation.
Figure 5.3.1
Refer to Fig. 5.3.1 and observe that since ${V}_{DS}={V}_{GS}={V}_{t}+{V}_{OV}$, we have
$${V}_{DS}>{V}_{OV}$$ 
and thus the MOSFET is operating in the saturation region. Thus, ignoring channellength modulation, we can write
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}$$ 
Substituting the given data, we obtain

(1) 
and

(2) 
Dividing Eq. (2) by Eq. (1), we obtain
$$\begin{array}{rcll}{\displaystyle \frac{9}{4}}& =& {\displaystyle \frac{{\left(0.7{V}_{t}\right)}^{2}}{{\left(0.6{V}_{t}\right)}^{2}}}& \text{}\\ \Rightarrow {\displaystyle \frac{3}{2}}& =& {\displaystyle \frac{0.7{V}_{t}}{0.6{V}_{t}}}& \text{}\end{array}$$which results in
$${V}_{t}=0.4\text{V}$$ 
Substituting for ${V}_{t}$ into Eq. (1) gives
$$\begin{array}{rcll}40& =& 200\times \left({\displaystyle \frac{W}{L}}\right)\times 0.04& \text{}\\ \Rightarrow {\displaystyle \frac{W}{L}}& =& 5& \text{}\end{array}$$5.4
An NMOS transistor for which ${k}_{n}=4$ mA/V ${}^{2}$ and ${V}_{t}=0.35$ V is operated with ${V}_{GS}={V}_{DS}=0.6$ V. What current results? To what value can ${V}_{DS}$ be reduced while maintaining the current unchanged? If the transistor is replaced with another fabricated in the same technology but with twice the width, what current results? For each of the two transistors when operated at small V _{DS}, what is the range of linear resistance ${r}_{DS}$ obtained when ${V}_{GS}$ is varied over the range 0.5 V to 1 V? Neglect channellength modulation.
Operation with ${V}_{DS}={V}_{GS}={V}_{t}+{V}_{OV}$ means ${V}_{DS}>{V}_{OV}$ and thus the MOSFET is in the saturation region. Thus, neglecting channellength modulation, we can write for ${I}_{D}$,
$$\begin{array}{rcll}{I}_{D}& =& {\displaystyle \frac{1}{2}}{k}_{n}{\left({V}_{GS}{V}_{t}\right)}^{2}& \text{}\\ & =& {\displaystyle \frac{1}{2}}\times 4\times {\left(0.60.35\right)}^{2}& \text{}\\ & =& 0.125\text{mA}& \text{}\end{array}$$The voltage ${V}_{DS}$ can be reduced to a value equal to ${V}_{OV}$ while the MOSFET remains in the saturation region, that is,
$${V}_{DS\text{min}}=0.60.35=0.25\text{V}$$ 
A transistor having twice the value of $W$ will have twice the value of ${k}_{n}$ and thus the current will be twice as large, that is,
$${I}_{D}=2\times 0.125=0.25\text{mA}$$ 
The linear resistance ${r}_{DS}$ is given by
$${r}_{DS}={\displaystyle \frac{1}{{k}_{n}\left({V}_{GS}{V}_{t}\right)}}$$ 
With ${V}_{t}=0.35$ V and with ${V}_{GS}$ varying over the range 0.5 V to 1 V, ${r}_{DS}$ will vary over the range
$${r}_{DS}={\displaystyle \frac{1}{0.15\phantom{\rule{2pt}{0ex}}}}\phantom{\rule{2pt}{0ex}}$$ 
For the ﬁrst device with ${k}_{n}=4$ mA/V, ${r}_{DS}$ will vary over the range
$${r}_{DS}={\displaystyle \frac{1}{0.15\times 4}}=1.67\text{k}\Omega $$ 
to
$${r}_{DS}={\displaystyle \frac{1}{0.65\times 4}}=0.38\text{k}\Omega $$ 
The wider device has ${k}_{n}=8$ mA/V and thus its ${r}_{DS}$ will vary over the range
$${r}_{DS}=0.833\text{k}\mathrm{\Omega}\text{to}\text{}0.192\text{k}\mathrm{\Omega}$$ 
5.5
An NMOS transistor is fabricated in a
0.13
$\mu $m process
having
${k}_{n}^{\text{'}}=500$
$\mu $A/V
${}^{2}$,
and
${V}_{A}^{\text{'}}=5$
V/
$\mu $m.
(a) If
$L=0.26$
$\mu $m
and
$W=2.6$
$\mu $m,
ﬁnd
${V}_{A}$
and
$\lambda $.
(b) If the device is operated at
${V}_{OV}=0.2$
V and
${V}_{DS}=0.65$
V, ﬁnd
${I}_{D}$.
(c) Find
${r}_{o}$
at the operating point speciﬁed in (b).
(d) If
${V}_{DS}$
is increased to 1.3 V, what is the corresponding change in
${I}_{D}$?
Do this two ways: using the expression for
${I}_{D}$
and using
${r}_{o}$.
Compare the results obtained.
(a)
$$\begin{array}{rcll}{V}_{A}& =& {V}_{A}^{\prime}L=5\times 0.26=1.3\text{V}& \text{}\\ \lambda & =& {\displaystyle \frac{1}{{V}_{A}}}={\displaystyle \frac{1}{1.3}}=0.77{\text{V}}^{1}& \text{}\end{array}$$ (b) Since ${V}_{DS}=0.65$ V is greater than ${V}_{OV}$, the NMOS transistor is operating in saturation. Thus, $$\begin{array}{rcll}{I}_{D}& =& {\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}& \text{}\\ & =& {\displaystyle \frac{1}{2}}\times 500\times {\displaystyle \frac{2.6}{0.26}}\times 0.{2}^{2}\times \left(1+0.77\times 0.65\right)& \text{}\\ & =& 150\phantom{\rule{2pt}{0ex}}& \text{}\end{array}$$(c)
$${r}_{o}={\displaystyle \frac{{V}_{A}}{{I}_{D}^{\text{'}}}}$$ 
where ${I}_{D}^{\text{'}}$ is the drain current without taking channellength modulation into account, thus
$$\begin{array}{rcll}{I}_{D}& =& {\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}& \text{}\\ & =& {\displaystyle \frac{1}{2}}\times 500\times {\displaystyle \frac{2.6}{0.26}}\times 0.{2}^{2}& \text{}\\ & =& 100\phantom{\rule{2pt}{0ex}}& \text{}\end{array}$$Hence,
$${r}_{o}={\displaystyle \frac{1.3\text{V}}{100\mu \text{A}}}={\displaystyle \frac{1.3\text{V}}{0.1\text{mA}}}=13\text{k}\Omega $$ 
(d) If ${V}_{DS}$ is increased to 1.3 V, ${I}_{D}$ becomes
$$\begin{array}{rcll}{I}_{D}& =& {\displaystyle \frac{1}{2}}\times 500\times {\displaystyle \frac{2.6}{0.26}}\times 0.{2}^{2}\left(1+0.77\times 1.3\right)& \text{}\\ & =& 200\mu \text{A}& \text{}\end{array}$$That is, ${I}_{D}$ increases by 50 $\mu \text{A}$. Alternatively, we can use ${r}_{o}$ to determine the increase in ${I}_{D}$ as
$$\begin{array}{rcll}\mathrm{\u25b3}{I}_{D}& =& {\displaystyle \frac{\mathrm{\u25b3}{V}_{DS}}{{r}_{o}}}& \text{}\\ & =& {\displaystyle \frac{0.65\text{V}}{13\text{k}\Omega}}=0.05\text{mA}=50\phantom{\rule{2pt}{0ex}}& \text{}\end{array}$$which is identical to the result obtained directly.
5.6
Figure 5.6.1
The PMOS transistor in Fig. 5.6.1 has
${V}_{tp}^{\prime}=0.5$
V,
${k}_{p}^{\prime}=100$
$\mu $A/V
${}^{2}$
, and
$W\mathrm{\u2215}L=10$.
(a) Find the range of
${v}_{G}$
for which the transistor conducts.
(b) In terms of
${v}_{G}$,
ﬁnd the range of
${v}_{D}$
for which the transistor operates in the triode region.
(c) In terms of
${v}_{G}$,
ﬁnd the range of
${v}_{D}$
for which the transistor operates in saturation.
(d) Find the value of
${v}_{G}$
and the range of
${v}_{D}$
for which the transistor operates in saturation with
${I}_{D}=20$
$\mu $A.
Assume
$\lambda =0$.
(e) If
$\mid \lambda \mid =0.2$
V
${}^{1}$,
ﬁnd
${r}_{o}$
at the operating point in (d).
(f) For
${V}_{OV}$
equal to that in (d) and
$\mathrm{\mid}\lambda \mathrm{\mid}=0.2$
V
${}^{1}$,
ﬁnd the value of
${I}_{D}$
at
${V}_{D}=1$
V and at
${V}_{D}=0$
V. Use these values to calculate the output resistance
${r}_{o}$
and compare the result to that found in (e).
Figure 5.6.1
$$\begin{array}{rcll}{V}_{tp}& =& 0.5\text{V},\phantom{\rule{19.04076pt"}{0ex}}& \text{}\\ W\mathrm{\u2215}L& =& 10& \text{}\end{array}$$
(a) For the transistor to conduct,
${v}_{G}$
must be lower than
${v}_{S}$
by at least
$\mid {V}_{tp}\mid $,
that is, by 0.5 V. Thus the transistor conducts for
${v}_{G}\le 1.80.5$,
or
${v}_{G}\le 1.3$
V.
(b) For the transistor to operate in the triode region, the drain voltage must be higher than the gate voltage by
at least
$\mid {V}_{tp}\mid $
volts, thus
$${v}_{D}\ge {v}_{G}+0.5\text{V}$$ 
(c) For the transistor to operate in the saturation region, the drain voltage cannot exceed the gate voltage by more than $\mid {V}_{tp}\mid $, that is,
$${v}_{D}\le {v}_{G}+0.5\text{V}$$ 
(d) When the transistor is operating in saturation, we obtain
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{0ex}{0ex}}$$ 
Substituting the given values, we obtain
$$\begin{array}{rcll}20& =& {\displaystyle \frac{1}{2}}\times 100\times 10{\left{V}_{OV}\right}^{2}& \text{}\\ \Rightarrow \mathrm{\mid}{V}_{OV}\mid & =& 0.2\phantom{\rule{0ex}{0ex}}& \text{}\end{array}$$which is obtained when
$$\begin{array}{rcll}{v}_{G}& =& {V}_{DD}{V}_{SG}& \text{}\\ & =& 1.8\left(\left{V}_{tp}\right+\left{V}_{OV}\right\right)& \text{}\\ & =& 1.8(0.5+0.2)=1.1\text{V}& \text{}\end{array}$$For this value of ${v}_{G}$, the range that ${v}_{D}$ is allowed to have while the transistor remains in saturation is
$${v}_{D}\le {v}_{G}+\left{V}_{tp}\right$$ 
that is,
$${v}_{D}\le 1.6\text{V}$$ 
(e)
$${r}_{o}={\displaystyle \frac{\mid {V}_{A}\mid}{{I}_{D}^{\prime}}}={\displaystyle \frac{1}{\left\lambda \right{I}_{D}^{\prime}}}\phantom{\rule{0ex}{0ex}}$$ 
where ${I}_{D}^{\prime}$ is the value of ${I}_{D}$ without channellength modulation taken into account, that is,
$$\begin{array}{rcll}{I}_{D}^{\prime}& =& {\displaystyle \frac{1}{2}}\phantom{\rule{0ex}{0ex}}& \text{}\\ & =& {\displaystyle \frac{1}{2}}\times 100\times 10\times 0.{2}^{2}=20\phantom{\rule{0ex}{0ex}}& \text{}\end{array}$$Thus,
$${r}_{o}={\displaystyle \frac{1}{0.2\times 20}}=0.25\text{M}\Omega $$ 
(f)
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}$$ 
At
${V}_{D}=1$
V, we have
${V}_{SD}=1.81=0.8$
V, and
${I}_{D}={\displaystyle \frac{1}{2}}\times 100\times 10\times 0.{2}^{2}\left(1+0.2\times 0.8\right)=23.2\phantom{\rule{2pt}{0ex}}$.
At ${V}_{D}=0$ V, we get ${V}_{SD}=1.80=1.8$ V, and ${I}_{D}={\displaystyle \frac{1}{2}}\times 100\times 10\times 0.{2}^{2}\phantom{\rule{2pt}{0ex}}$
Thus, for
$$\mathrm{\u25b3}{V}_{SD}=1.80.8=1\text{V},$$ 
the current changes by
$$\mathrm{\u25b3}{I}_{D}=27.223.2=4\phantom{\rule{2pt}{0ex}}$$ 
indicating that the output resistance ${r}_{o}$ is
$${r}_{o}={\displaystyle \frac{\mathrm{\u25b3}{V}_{D}}{\mathrm{\u25b3}{I}_{D}}}={\displaystyle \frac{1\text{V}}{4\phantom{\rule{2pt}{0ex}}}}=0.25\text{M}\Omega $$ 
which is the same value found in (e).
Section 5.3: MOSFET Circuits at DC
D5.7
Figure 5.7.1
Figure 5.7.2
The NMOS transistor in the circuit in Fig. 5.7.1 has
${V}_{tn}=0.5$ V,
${k}_{n}^{\text{'}}=400$
$\mu $A/V
${}^{2}$,
$W\mathrm{\u2215}L=10$, and
$\lambda =0$.
(a) Design the circuit (i.e., find the required values for
${R}_{S}$
and
${R}_{D}$)
to obtain
${I}_{D}=180$
$\mu $A
and
${V}_{D}=+0.5$
V. Find the voltage
${V}_{S}$
that results.
(b) If
${R}_{S}$
is replaced with a constantcurrent source
$I$,
as shown in Fig. 5.7.2, what must the value of
$I$
be to obtain the same operating conditions as in (a)?
(c) What is the largest value to which
${R}_{D}$
can be increased while the transistor remains in saturation?
Figure 5.7.1
(a) Refer to the circuit in Fig 5.7.1. For ${V}_{D}=+0.5$ V, the transistor is operating in saturation since ${V}_{D}\mathrm{}{V}_{G}$. Thus,
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}$$ 
where we have utilized the given information that $\lambda =0$. To obtain ${I}_{D}=180\phantom{\rule{2pt}{0ex}}$, the required ${V}_{OV}$ can be found from
$$\begin{array}{rcll}180& =& {\displaystyle \frac{1}{2}}\times 400\times 10{V}_{OV}^{2}& \text{}\\ \Rightarrow {V}_{OV}& =& 0.3\text{V}& \text{}\end{array}$$The value of ${V}_{GS}$ can be found as
$${V}_{GS}={V}_{tn}+{V}_{OV}=0.5+0.3=0.8\text{V}$$ 
from which ${V}_{S}$ can be determined as
$${V}_{S}={V}_{G}{V}_{GS}=00.8=0.8\text{V}$$ 
The required value of ${R}_{S}$ can now be found from
$$\begin{array}{rcll}{R}_{S}& =& {\displaystyle \frac{{V}_{S}({V}_{SS})}{{I}_{D}}}& \text{}\\ & =& {\displaystyle \frac{0.8(1)}{180\phantom{\rule{0ex}{0ex}}}}={\displaystyle \frac{0.2\phantom{\rule{0ex}{0ex}}}{0.18\text{mA}}}=1.11\text{k}\Omega & \text{}\end{array}$$Finally, the value of ${R}_{D}$ can be found from
$$\begin{array}{rcll}{R}_{D}& =& {\displaystyle \frac{{V}_{DD}{V}_{D}}{{I}_{D}}}& \text{}\\ & =& {\displaystyle \frac{10.5}{0.18\text{mA}}}=2.78\text{k}\Omega & \text{}\end{array}$$
Figure 5.7.3
Figure 5.7.3 shows the designed circuit with the component values and the values of current and
voltages.
(b) If
${R}_{S}$
is replaced by a constantcurrent source
$I$, as shown in Fig. 5.7.2,
the value of
$I$ must be equal
to the desired value of
${I}_{D}$,
that is,
$180\phantom{\rule{2pt}{0ex}}$
or
$0.18\text{mA}$.
Figure 5.7.2
(c) Refer to Fig. 5.7.1.
As
${R}_{D}$ is increased,
${V}_{D}$
decreases as
Eventually, ${V}_{D}$ falls below ${V}_{G}$ by ${V}_{tn}$ at which point the transistor leaves the saturation region and enters the triode region. This occurs at
$${V}_{D}={V}_{G}{V}_{tn}=00.5=0.5\text{V}$$ 
The corresponding value of ${R}_{D}$ can be found from
$$\begin{array}{rcll}0.5& =& 10.18\times {R}_{D}& \text{}\\ \Rightarrow {R}_{D}& =& 8.33\text{k}\Omega & \text{}\end{array}$$D5.8
Figure 5.8.1
The PMOS transistor in the circuit in
Fig. 5.8.1
has
${V}_{tp}=0.5$
V,
${k}_{p}^{\text{'}}=100$
$\mu $A/V
${}^{2}$,
$W\mathrm{\u2215}L=20$, and
$\lambda =0$.
(a) Find
${R}_{S}$
and
${R}_{D}$
to obtain
${I}_{D}=0.1$
mA and
${V}_{D}=0$
V.
(b) What is the largest
${R}_{D}$
for which the transistors remains in saturation. At this value of
${R}_{D}$,
what is the voltage at the drain,
${V}_{D}$?
Figure 5.8.1
(a) With ${V}_{D}=0$ V, the transistor will be operating in the saturation region since ${V}_{D}={V}_{G}$. Thus,
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{0ex}{0ex}}$$ 
where we have taken into account that $\lambda =0$ as stated. To obtain ${I}_{D}=0.1\text{mA}=100\phantom{\rule{2pt}{0ex}}$, the required value of $\mid {V}_{OV}\mid $ can be found as follows:
$$\begin{array}{rcll}100& =& {\displaystyle \frac{1}{2}}\times 100\times 20{\left{V}_{OV}\right}^{2}& \text{}\\ \Rightarrow \mathrm{\mid}{V}_{OV}\mathrm{\mid}& =& 0.316\phantom{\rule{0ex}{0ex}}& \text{}\end{array}$$The value of ${V}_{SG}$ can now be found as
$${V}_{SG}=\mathrm{\mid}{V}_{tp}\mathrm{\mid}+\mathrm{\mid}{V}_{OV}\mathrm{\mid}=0.5+0.316=0.816\text{V}$$ 
Thus,
$${V}_{S}={V}_{SG}=0.816\text{V}$$ 
The required value of ${R}_{S}$ can be determined from
$$\begin{array}{rcll}{R}_{S}& =& {\displaystyle \frac{{V}_{DD}{V}_{S}}{{I}_{D}}}& \text{}\\ & =& {\displaystyle \frac{10.816}{0.1}}=1.84\text{k}\Omega & \text{}\end{array}$$Finally, the required value of ${R}_{D}$ can be found from
$$\begin{array}{rcll}{R}_{D}& =& {\displaystyle \frac{{V}_{D}\left({V}_{SS}\right)}{{I}_{D}}}& \text{}\\ & =& {\displaystyle \frac{0\left(1\right)}{0.1}}=10\text{k}\Omega & \text{}\end{array}$$The designed circuit with component values and current and voltage values is shown in Figure 5.8.2. The reader can check the calculations directly on the circuit diagram.
Figure 5.8.2
(b) Refer to Figure 5.8.1. The transistor remains in saturation as long as ${V}_{D}$ does not increase above ${V}_{G}$ by more than $\mid {V}_{tp}\mid $. Since ${V}_{G}=0$ and $\mathrm{\mid}{V}_{tp}\mathrm{\mid}=0.5$ V, the maximum allowable value of ${V}_{D}$ is
$${V}_{D\text{max}}=+0.5\text{V}$$ 
To obtain this value of ${V}_{D}$, ${R}_{D}$ must be increased to
$${R}_{D}={\displaystyle \frac{{V}_{D\text{max}}\left(1\right)}{0.1\text{mA}}}={\displaystyle \frac{0.5+1}{0.1}}=15\text{k}\Omega $$ 
5.9
Figure 5.9.1
The NMOS transistor in the circuit in Fig. 5.9.1 has ${V}_{t}=0.5$ V, ${k}_{n}^{}=10$ mA/V ${}^{2}$, and $\lambda =0$. Analyze the circuit to determine the currents through all branches and to find the voltages at all nodes.
Figure 5.9.1
The current $I$ through the voltage divider ${R}_{G1}$− ${R}_{G2}$ can be found as
$$\begin{array}{rcll}I& =& {\displaystyle \frac{{V}_{DD}}{{R}_{G1}+{R}_{G2}}}& \text{}\\ & =& {\displaystyle \frac{5\text{V}}{3\text{M}\Omega +2\text{M}\Omega}}={\displaystyle \frac{5\text{V}}{5\text{M}\Omega}}=1\phantom{\rule{2pt}{0ex}}& \text{}\end{array}$$The voltage ${V}_{G}$ at the gate can now be found as
$${V}_{G}=I{R}_{G2}=1\phantom{\rule{2pt}{0ex}}$$ 
The voltage ${V}_{S}$ is given by
$$\begin{array}{rcll}{V}_{S}& =& {V}_{G}{V}_{GS}={V}_{G}\left({V}_{t}+{V}_{OV}\right)& \text{}\\ & =& 2\left(0.5+{V}_{OV}\right)& \text{}\end{array}$$

(1) 
But ${V}_{S}$ can be expressed in terms of ${I}_{D}$ as
$${V}_{S}={I}_{D}{R}_{S}={I}_{D}\times 6.5=6.5\phantom{\rule{0ex}{0ex}}$$ 
Thus,

(2) 
We do not know whether the transistor is operating in the saturation region or in the triode region. Therefore, we must make an assumption about the region of operation, complete the analysis, and then use the results obtained to check the validity of our assumption. If our assumption proves valid, our work is done. Otherwise, we must redo the analysis assuming the other mode of operation. Since the $i$ $v$ relationships that describe the saturationregion operation are simpler than those that apply in the triode region, we normally assume operation in the saturation region, unless of course there is an indication of triodemode operation.
Assuming that the transistor in the circuit of Figure 5.9.1 is operating in saturation, we can write
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}$$ 

(3) 
Substituting for ${I}_{D}$ from Eq. (3) into Eq. (2) gives
$$6.5\times 5{V}_{OV}^{2}=1.5{V}_{OV}$$ 
which can be rearranged into the form
$$32.5{V}_{OV}^{2}+{V}_{OV}1.5=0$$ 
Solving this quadratic equation yields
$${V}_{OV}=0.2\text{V}\text{or}\phantom{\rule{2pt}{0ex}}$$ 
Obviously, the negative value is physically meaningless and can be discarded. Thus,
$${V}_{OV}=0.2\text{V}$$ 
and
$${I}_{D}=5{V}_{OV}^{2}=5\times 0.{2}^{2}=0.2\text{mA}$$ 
We are now ready to check the validity of our assumption of saturation mode operation. Referring to the circuit in Figure 5.9.1, we can find the voltage ${V}_{D}$ as follows:
$$\begin{array}{rcll}{V}_{D}& =& {V}_{DD}{I}_{D}{R}_{D}& \text{}\\ & =& 50.2\times 12.5=2.5\text{V}& \text{}\end{array}$$which is greater than ${V}_{G}\phantom{\rule{2pt}{0ex}}$ conﬁrming that the transistor is operating in saturation, as assumed. Figure 5.9.2 shows the circuit together with the values of all node voltages and branch currents. The reader is encouraged to check their results by doing a few calculations directly on the circuit.
Figure 5.9.2
5.10
Figure 5.10.1
For the circuit in Fig. 5.10.1, the NMOS transistor has ${V}_{tn}=0.5$ V, ${k}_{n}^{}=10$ mA/V ${}^{2}$, and ${\lambda}_{n}=0$, and the PMOS transistor has ${V}_{tp}=0.5$ V, ${k}_{p}^{}=12.5$ mA/V ${}^{2}$, and $\mathrm{\mid}{\lambda}_{p}\mathrm{\mid}=0$. Observe that ${Q}_{1}$ and its surrounding circuit is the same as the circuit analyzed in Problem 5.9 (Fig. 5.9.1), and you may use the results found in the solution to that problem here. Analyze the circuit to determine the currents in all branches and the voltages at all nodes.
From Fig. 5.10.1 in the problem statement we observe that transistor ${Q}_{1}$ together with its associated resistors is an identical circuit to that analyzed in the solution to Problem 5.9 (see Fig. 5.9.1). Since the gate terminal of ${Q}_{2}$ draws zero current, transistor ${Q}_{2}$ together with its associated resistances do not change the currents and voltages in ${Q}_{1}$ and its associated resistances. Thus, we need to only concern ourselves with the analysis of the part of the circuit shown in Figure 5.10.2, where ${V}_{GS}$ is found from
$${V}_{G2}={V}_{D1}=2.5\text{V}$$ 
Figure 5.10.2
Since we do not know whether ${Q}_{2}$ is operating in saturation or in the triode region, we shall assume saturationmode operation and, of course, we will have to check the validity of this assumption. We can now write
$\begin{array}{cll}{I}_{D2}& =& {\displaystyle \frac{1}{2}}{k}_{p}{\left{V}_{OV2}\right}^{2}\\ & =& {\displaystyle \frac{1}{2}}\times 12.5{\left{V}_{OV2}\right}^{2}\end{array}$ 
Thus,

(1) 
Another relationship between ${I}_{D2}$ and $\mid {V}_{OV2}\mid $ can be obtained as follows:
$$\begin{array}{rcll}{V}_{S2}& =& {V}_{G2}+{V}_{SG2}& \text{}\\ & =& {V}_{G2}+\left(\mathrm{\mid}{V}_{tp}\mathrm{\mid}+\mathrm{\mid}{V}_{OV2}\mathrm{\mid}\right)& \text{}\\ & =& 2.5+0.5+\mathrm{\mid}{V}_{OV2}\mathrm{\mid}& \text{}\\ & =& 3+\mathrm{\mid}{V}_{OV2}\mathrm{\mid}& \text{}\end{array}$$But

(2) 
Equating ${I}_{D2}$ from Eqs. (1) and (2) results in
$$6.25\mathrm{\mid}{V}_{OV2}{\mathrm{\mid}}^{2}={\displaystyle \frac{2\mathrm{\mid}{V}_{OV2}\mathrm{\mid}}{7.2}}$$ 
which can be rearranged into the form
$$45\mathrm{\mid}{V}_{OV2}{\mathrm{\mid}}^{2}+\mathrm{\mid}{V}_{OV2}\mathrm{\mid}2=0$$ 
This quadratic equation can be solved to obtain
$$\mid {V}_{OV2}\mathrm{\mid}=0.2\text{V}\text{or}\phantom{\rule{2pt}{0ex}}$$ 
Obviously, the negative solution is physically meaningless, thus
$$\mathrm{\mid}{V}_{OV2}\mathrm{\mid}=0.2\text{V}$$ 
and
$${I}_{D2}=6.25\times 0.{2}^{2}=0.25\text{mA}$$ 
We are now ready to check the validity of our assumption of saturationmode operation. We can do this by ﬁnding ${V}_{D2}$:
$${V}_{D2}={I}_{D2}{R}_{D2}=0.25\times 8=2\text{V}$$ 
which is lower than the voltage at the gate ( V _{G2} = 2.5 V), confirming saturationmode operation. The voltage V _{S2} can be found as
$${V}_{S2}={V}_{DD}{I}_{D2}{R}_{S2}=50.25\times 7.2=+3.2\text{V}$$ 
Figure 5.10.3
Finally, Fig. 5.10.3 shows the complete circuit with all currents and voltages. The values associated with ${Q}_{1}$ are those obtained in the solution for Problem 5.9. The reader is urged to make a few quick checks on the results displayed in Fig. 5.10.3.
D5.11
Figure 5.11.1
Design the circuit in Fig. 5.11.1 to obtain $I=1$ $\mu $A, ${I}_{D}=0.5$ mA, ${V}_{S}=2$ V, and ${V}_{D}=5$ V. The NMOS transistor has ${V}_{t}=0.5$ V, ${k}_{n}=4$ mA/V ${}^{2}$, and $\lambda =0$.
Figure 5.11.1
Refer to Fig. 5.11.1. We assume that the transistor is operating in the saturation mode, thus
$${I}_{D}={\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}$$ 
where we have taken account of the stated value $\lambda =0$. To obtain ${I}_{D}=0.5$ mA, the required value of ${V}_{OV}$ can be found from
$$\begin{array}{rcll}0.5& =& {\displaystyle \frac{1}{2}}\times 4{V}_{OV}^{2}& \text{}\\ \Rightarrow {V}_{OV}& =& 0.5\text{V}& \text{}\end{array}$$Now, since
$${V}_{DS}={V}_{D}{V}_{S}=52=3\text{V}$$ 
is greater than ${V}_{OV}$, the MOSFET is operating in saturation, as assumed. The required value of ${R}_{S}$ can be determined as follows:
$${R}_{S}={\displaystyle \frac{{V}_{S}}{{I}_{D}}}={\displaystyle \frac{2}{0.5}}=4\text{k}\Omega $$ 
and the required value of ${R}_{D}$ can be determined as follows:
$${R}_{D}={\displaystyle \frac{{V}_{DD}{V}_{D}}{{I}_{D}}}={\displaystyle \frac{105}{0.5}}=10\text{k}\Omega $$ 
The voltage at the gate ${V}_{G}$ is found as
$${V}_{G}={V}_{GS}+{V}_{S}$$ 
where
$${V}_{GS}={V}_{t}+{V}_{OV}=0.5+0.5=1\text{V}$$ 
Thus,
$${V}_{G}=1+2=3\text{V}$$ 
The resistance ${R}_{G1}$ can be found as follows:
$${R}_{G1}={\displaystyle \frac{{V}_{DD}{V}_{G}}{{I}_{}}}={\displaystyle \frac{103}{1\phantom{\rule{2pt}{0ex}}}}=7\text{M}\Omega $$ 
and, ﬁnally, ${R}_{G2}$ can be found as
$${R}_{G2}={\displaystyle \frac{{V}_{G}}{{I}_{}}}={\displaystyle \frac{3\text{V}}{1\phantom{\rule{2pt}{0ex}}}}=3\text{M}\Omega $$ 
5.12
Figure 5.12.1
The transistors in the circuits of Fig. 5.12.1 have $\mathrm{\mid}{V}_{t}\mathrm{\mid}=0.5$ V, ${k}_{n}={k}_{p}=20$ mA/V ${}^{2}$, and $\lambda =0$. Also, $I=0.9$ mA. For each circuit ﬁnd ${v}_{O}$ as a function of ${v}_{I}$ assuming the transistors are operating in saturation. In each case ﬁnd the allowable ranges of ${v}_{O}$ and ${v}_{I}$. Assume that the minimum voltage ${V}_{CS}$ required across each current source is 0.3 V.
(a)
Figure 5.12.1(a)
$${v}_{O}={v}_{I}{V}_{GS}$$ 
where
$${V}_{GS}={V}_{t}+{V}_{OV}$$ 
and ${V}_{OV}$ can be found from
$${I}_{D}=I={\displaystyle \frac{1}{2}}\phantom{\rule{2pt}{0ex}}$$ 
Thus,
$$\begin{array}{rcll}0.9& =& {\displaystyle \frac{1}{2}}\times 20\phantom{\rule{2pt}{0ex}}& \text{}\\ \Rightarrow {V}_{OV}& =& 0.3\text{V}& \text{}\end{array}$$and
$${V}_{GS}=0.5+0.3=0.8\text{V}$$ 
Thus,

(1) 
The highest value that ${v}_{O}$ can have while the transistor remains in saturation is limited by the need to keep ${v}_{DS}$ at least equal to ${V}_{OV}$, thus
$${v}_{O\text{max}}=2.5{V}_{OV}=2.2\text{V}$$ 
The lowest value that ${v}_{O}$ can have is limited by the need to keep the voltage across the current source ${V}_{CS}$ at least equal to 0.3 V, thus
$${v}_{O\text{min}}=2.5+0.3=2.2\text{V}$$ 
Thus, the allowable range of ${v}_{O}$ is
$$2.2\text{V}\le {v}_{O}\le +2.2\text{V}$$ 
and the corresponding allowable range of ${v}_{I}$ can be found using Eq. (1) as
$$1.4\text{V}\le {v}_{I}\le +3\text{V}$$ 
(b)
Figure 5.12.1(b)
$${v}_{O}={v}_{I}+{V}_{SG}$$ 
where
$${V}_{SG}=\mathrm{\mid}{V}_{t}\mathrm{\mid}+\mathrm{\mid}{V}_{OV}\mathrm{\mid}$$ 
and $\mid {V}_{OV}\mid $ can be found from
$$\begin{array}{rcll}{I}_{D}& =& I={\displaystyle \frac{1}{2}}{k}_{p}{\left{V}_{OV}\right}^{2}& \text{}\\ 0.9& =& {\displaystyle \frac{1}{2}}\times 20{\left{V}_{OV}\right}^{2}& \text{}\\ \mathrm{\Rightarrow}\mathrm{\mid}{V}_{OV}\mid & =& 0.3\text{V}& \text{}\end{array}$$Thus,
$${V}_{SG}=0.5+0.3=0.8\text{V}$$ 
and,

(2) 
The highest value that ${v}_{O}$ can have is limited by the need to keep the voltage ${V}_{CS}$ across the current source to at least 0.3 V, thus
$${v}_{O\text{max}}=2.50.3=2.2\text{V}$$ 
The lowest value that ${v}_{O}$ can have is limited by the need to keep the voltage ${v}_{SD}$ to a value at least equal to $\mid {V}_{OV}\mid $, thus
$${v}_{O\text{min}}=2.5+0.3=2.2\text{V}$$ 
Thus, the allowable range of ${v}_{O}$ is
$$2.2\text{V}\le {v}_{O}\le +2.2\text{V}$$ 
The corresponding range of ${v}_{I}$ can be determined using Eq. (2) as
$$3\text{V}\le {v}_{I}\le +1.4\text{V}$$ 
(c)
Figure 5.12.1(c)
From the results of (a) and (b), we know that
$${V}_{GS1}={V}_{SG2}=0.8\text{V}$$ 
The voltage ${v}_{O}$ can be found as follows:
$$\begin{array}{rcll}{v}_{O}& =& {v}_{I}{V}_{GS1}+{V}_{GS2}& \text{}\\ & =& {v}_{I}0.8+0.8& \text{}\end{array}$$Thus,

(3) 
The highest value of ${v}_{O}$ is determined by the need to keep the voltage ${V}_{CS}$ across the current source $I$ of ${Q}_{2}$ at least equal to 0.3 V. Thus,
$${v}_{O\text{max}}=2.50.3=+2.2\text{V}$$ 
At this value, the voltage at the source of ${Q}_{1}$ is
$${v}_{S1}=2.20.8=+1.4\text{V}$$ 
which is an allowed value as we determined in (a) above.
The lowest value of ${v}_{O}$ can be determined by the need to maintain a minimum ${v}_{SD}$ across ${Q}_{2}$ of value equal to $\mid {V}_{OV}\mathrm{\mid}=0.3$ V. This would imply that ${v}_{O}$ can be as low as $2.5+0.3=2.2$ V. However, ${v}_{O}=2.2$ V would require ${v}_{S1}$ to be ${v}_{S1}=2.2{V}_{SG}=2.20.8=3$ V, which is not within the allowable range for ${v}_{S1}$ [see (a) above]. It follows that the lowest allowable value of ${v}_{O}$ is determined by the lowest allowable value at the source of ${Q}_{1}$:
$$\begin{array}{rcll}{v}_{O\text{min}}& =& {v}_{S1\text{min}}+{V}_{SG}& \text{}\\ & =& 2.2+0.8& \text{}\\ & =& 1.4\text{V}& \text{}\end{array}$$Thus, the allowable range of ${v}_{O}$ is
$$1.4\text{V}\le {v}_{O}\le +2.2\text{V}$$ 
and using Eq. (3), the allowable range of ${v}_{I}$ can be found as
$$1.4\text{V}\le {v}_{I}\le 2.2\text{V}$$ 
(d)
Figure 5.12.1(d)
Following a procedure identical to that we used for (c) above, we can show that here

(4) 
and that the allowable range at the output is
$$2.2\text{V}\le {v}_{O}\le +1.4\text{V}$$ 
and at the input
$$2.2\text{V}\le {v}_{I}\le +1.4\text{V}$$ 